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A sample rate converter(SRC) is designed to adjust the sampling rate ofdigital signals flexibly for different application requirements in thebroadband signal processing system. In this paper, a novel parallel-serialstructure is proposed to improve the bandwidth and flexibility of SRC. The coreof this structure is a parallel decimation filter followed by a serialcounterpart, the parallel part is designed to process high sampling rate datastreams, and the serial part provides high flexibility in decimation factorconfiguration. A typical combination of cascaded integral comb filter(CIC) andhalfband filter is utilized in this structure, the serial recursive loop whichlimits the processing ability of the CIC filter is transformed into aparallel-pipeline recursive structure. In addition, the symmetry property andzero coefficient of the halfband filter are exploited with the polyphase filterstructure to reduce resource utilization and design complexity. In themeantime, the decimation factor of the CIC filter can be adjusted flexibly in awide range, which is used to improve the system configuration flexibility. Thisparallel-serial SRC structure was implemented on Xilinx KU115 series fieldprogrammable gate array(FPGA), and then applied in a synthetic instrumentsystem. The experiment results demonstrate that the proposed schemesignificantly improves the performance of SRC in bandwidth and flexibility.

Wideband Sample Rate Converter Using Cascaded Parallel-serial Structure for Synthetic Instrumentation