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This paper introduces a new paradigm of chip design for the semi-conductorindustry called Data-Rich Analytics Based Computer Architecture (BRYT). Thegoal is to enable monitoring chip hardware behavior in the field, at real-timespeeds with no slowdowns, with minimal power overheads and obtain insights onchip behavior and workloads. The paradigm is motivated by the end of Moore'sLaw and Dennard Scaling which necessitates architectural efficiency as themeans for improved capability for the next decade or two. This paper implementsthe first version of the paradigm with a system architecture and the concept ofan analYtics Processing Unit (YPU). We perform 4 case studies, and implement anRTL level prototype. Across the case studies we show a YPU with area overhead<3% at 7nm, and overall power consumption of <25 mW is able to createpreviously inconceivable data PICS stacks of arbitrary programs, evaluatinginstruction prefetchers in the wild before deployment, fine-grainedcycle-by-cycle utilization of hardware modules, and histograms of tensor-valuedistributions of DL models.

BRYT: Data Rich Analytics Based Computer Architecture for A New Paradigm of Chip Design to Supplant Moore's Law