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Motivated by the end of Moore's Law and Dennard Scaling which necessitatearchitectural efficiency as the means for improved capability for the nextdecade or two, this paper introduces a new data-rich paradigm of chip designfor the semi-conductor industry. The goal is to enable monitoring chip hardwarebehavior in the field, at real-time speeds with no slowdowns, with minimalpower overheads and obtain insights on chip behavior and workloads. We positthat, such extensive amounts of data would allow better and more capablearchitectures addressing three problems: obfuscated hardware, obfuscatedsoftware, and inability of A/B testing for hardware ideas. This paperimplements the first version of the paradigm with a system architecture and theconcept of an analYtics Processing Unit (YPU). We perform 4 case studies, andimplement an RTL level prototype. Across the case studies we show a YPU witharea overhead $<1 \%$ at 7nm, and overall power consumption of $<25 mW$ is ableto create previously inconceivable analysis: per-instruction cycles stacks ofarbitrary programs, evaluating instruction prefetchers in the wild beforedeployment, fine-grained cycle-by-cycle utilization of hardware modules, andhistograms of tensor-value distributions of DL models.

BRYT: Data Rich Analytics Based Computer Architecture for A New Paradigm of Chip Design