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Quantum computation holds the promise of solving computational problems whichare believed to be classically intractable. However, in practice, quantumdevices are still limited by their relatively short coherence times andimperfect circuit-hardware mapping. In this work, we present theparallelization of pre-calibrated pulses at the hardware level as aneasy-to-implement strategy to optimize quantum gates. Focusing on $R_{ZX}$gates, we demonstrate that such parallelization leads to improved fidelity andgate time reduction, when compared to serial concatenation. As measured byCycle Benchmarking, our most modest fidelity gain was from 98.16(7)% to99.15(3)% for the application of two $R_{ZX}(\pi/2)$ gates with one sharedqubit. We show that this strategy can be applied to other gates like the CNOTand CZ, and it may benefit tasks such as Hamiltonian simulation problems,amplitude amplification, and error-correction codes.

Improving fidelity of multi-qubit gates using hardware-level pulse parallelization