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Resistive Random Access Memory (ReRAM) based Processing In Memory (PIM)Accelerator has emerged as a promising computing architecture for memoryintensive applications, such as Deep Neural Networks (DNNs). However, due toits immaturity, ReRAM devices often suffer from various reliability issues,which hinder the practicality of the PIM architecture and lead to a severedegradation in DNN accuracy. Among various reliability issues, device variationand offset current from High Resistance State (HRS) cell have been consideredas major problems in a ReRAM based PIM architecture. Due to these problems, thethroughput of the ReRAM based PIM is reduced as fewer wordlines are activated.In this paper, we propose VECOM, a novel approach that includes a variationresilient encoding technique and an offset compensation scheme for a robustReRAM based PIM architecture. The first technique (i.e., VECOM encoding) isbuilt based on the analysis of the weight pattern distribution of DNN models,along with the insight into the ReRAM's variation property. The secondtechnique, VECOM offset compensation, tolerates offset current in PIM bymapping the conductance of each Multi level Cell (MLC) level added with aspecific offset conductance. Experimental results in various DNN models anddatasets show that the proposed techniques can increase the throughput of thePIM architecture by up to 9.1 times while saving 50% of energy consumptionwithout any software overhead. Additionally, VECOM is also found to endure lowR ratio ReRAM cell (up to 7) with a negligible accuracy drop.

VECOM: Variation Resilient Encoding and Offset Compensation Schemes for Reliable ReRAM Based DNN Accelerator