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High-level synthesis (HLS) tools have provided significant productivityenhancements to the design flow of digital systems in recent years, resultingin highly-optimized circuits, in terms of area and latency. Given the evolutionof hardware attacks, which can render them vulnerable, it is essential toconsider security as a significant aspect of the HLS design flow. Yet the needto evaluate a huge number of functionally equivalent de-signs of the HLS designspace challenges hardware security evaluation methods (e.g., fault injection -FI campaigns). In this work, we propose an evaluation methodology of hardwaresecurity properties of HLS-produced designs using state-of-the-art Graph NeuralNetwork (GNN) approaches that achieves significant speedup and betterscalability than typical evaluation methods (such as FI). We demonstrate theproposed methodology on a Double Modular Redundancy (DMR) coun-termeasureapplied on an AES SBox implementation, en-hanced by diversifying the redundantmodules through HLS directives. The experimental results show that GNNs can beefficiently trained to predict important hardware security met-rics concerningfault attacks (e.g., critical and detection error rates), by using regression.The proposed method predicts the fault vulnerability metrics of the HLS-baseddesigns with high R-squared scores and achieves huge speedup compared to faultinjection once the training of the GNN is completed.

On the Prediction of Hardware Security Properties of HLS Designs Using Graph Neural Networks