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This project focuses on making a RISC-V CPU Core using the Logisim software.RISC-V is significant because it will allow smaller device manufacturers tobuild hardware without paying royalties and allow developers and researchers todesign and experiment with a proven and freely available instruction setarchitecture. RISC-V is ideal for a variety of applications from IOTs toEmbedded systems such as disks, CPUs, Calculators, SOCs, etc. RISC-V(ReducedInstruction Set Architecture) is an open standard instruction set architecture(ISA) based on established reduced instruction set computer (RISC) principles.Unlike most other ISA designs, the RISC-V ISA is provided under open sourcelicenses that do not require fees to use.

32-Bit RISC-V CPU Core on Logisim