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Large spiking neural networks (SNNs) require ultra-low power and lowvariability hardware for neuromorphic computing applications. Recently, aband-to-band tunneling-based (BTBT) integrator, enabling sub-kHz operation ofneurons with area and energy efficiency, was proposed. For an ultra-low powerimplementation of such neurons, a very low BTBT current is needed, sominimizing current without degrading neuronal properties is essential. Lowvariability is needed in the ultra-low current integrator to avoid networkperformance degradation in a large BTBT neuron-based SNN. To address this, weconducted design space and variability analysis in TCAD, utilizing awell-calibrated TCAD deck with experimental data from GlobalFoundries 32nmPD-SOI MOSFET. First, we discuss the physics-based explanation of the tunnelingmechanism. Second, we explore the impact of device design parameters on SOIMOSFET performance, highlighting parameter sensitivities to tunneling current.With device parameters' optimization, we demonstrate a ~20x reduction in BTBTcurrent compared to the experimental data. Finally, a variability analysis thatincludes the effects of random dopant fluctuations (RDF), oxide thicknessvariability (OTV), and channel-oxide interface traps DIT in the BTBT, SS, andON regimes of operation is shown. The BTBT regime shows high sensitivity to theRDF and OTV as any variation in them directly modulates the tunnel length orthe electric field at the drain-channel junction, whereas minimal sensitivityto DIT is observed.

Design Space and Variability Analysis of SOI MOSFET for Ultra-Low Power Band-to-Band Tunneling Neurons