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Quantum processors using superconducting qubits suffer from dielectric lossleading to noise and dissipation. Qubits are usually designed as largecapacitor pads connected to a non-linear Josephson junction (or SQUID) by asuperconducting thin metal wiring. Here, we report on finite-element simulationand experimental results confirming that more than 50% of surface loss intransmon qubits can originated from Josephson junctions wiring and can limitqubit relaxation time. Extracting dielectric loss tangents capacitor pads andwiring based on their participation ratios, we show dominant surface loss ofwiring can occur for real qubits designs. Then, we simulate a qubit coupled toa bath of individual TLS defects and show that only a small fraction (~18%) ofcoupled defects is located within the wiring interfaces, however, theircoupling strength is much higher due to stronger electromagnetic field.Finally, we fabricate six tunable floating transmon qubits and experimentallydemonstrate up to 20% improvement in qubit quality factor by wiring designoptimization.

Wiring surface loss of a superconducting transmon qubit