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This paper presents the design and characterization of a monolithicintegrated circuit (IC) including digital silicon photomultipliers (dSiPMs)arranged in a 32$~\times~$32 pixel matrix at 70$~\mu$m pitch. The IC providesper-quadrant time stamping and hit-map readout, and is fabricated in a standard150-nm CMOS technology. Each dSiPM pixel consists of four single-photonavalanche diodes (SPADs) sharing a quenching and subsequent processingcircuitry and has a fill factor of 30$~\%$. A sub-100$~$ps precision, 12-bittime-to-digital converter (TDC) provides timestamps per quadrant with anacquisition rate of 3$~$MHz. Together with the hit map, the total sustaineddata throughput of the IC amounts to 4$~$Gbps. Measurements obtained in a dark,temperature-stable environment as well as by using a pulsed laser environmentshow the full dSiPM-IC functionality. The dark-count rate (DCR) as function ofthe overvoltage and temperature, the TDC resolution, differential and integralnonlinearity (DNL/INL) as well as the propagation-delay variations across thematrix are presented. With aid of additional peripheral test structures, themain building blocks are characterized and key parameters are presented.

Monolithic MHz-frame rate digital SiPM-IC with sub-100 ps precision and 70$~\mu$m pixel pitch