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Although fabrication capabilities of Silicon Dangling Bonds have rapidlyadvanced from manual labor-driven laboratory work to automated manufacturing injust recent years, sub-nanometer substrate defects still pose a hindrance toproduction due to the need for atomic precision. In essence, unpassivated ormissing surface atoms, contaminants, and structural deformations disturb thefabricated logic or prevent its realization altogether. Moreover, designautomation techniques in this domain have not yet adopted any defect-awarebehavior to circumvent the present obstacles. In this paper, we derive asurface defect model for design automation from experimentally verified defecttypes that we apply to identify sensitivities in an established gate library inan effort to generate more robust designs. Furthermore, we present an automaticplacement and routing algorithm that considers scanning tunneling microscopedata obtained from physical experiments to lay out dot-accurate circuitry thatis resilient against the presence of atomic surface defects. This culminates ina holistic evaluation on surface data of varying defect rates that enables usto quantify the severity of such defects. We project that fabricationcapabilities must achieve defect rates of around 0.1 %, if charged defects canbe completely eliminated, or < 0.1 %, otherwise. This realization sets the pacefor future efforts to scale up this promising circuit technology.

Atomic Defect-Aware Physical Design of Silicon Dangling Bond Logic on the H-Si(100)2x1 Surface