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Processors using the open RISC-V ISA are finding increasing adoption in theembedded world. Many embedded use cases have real-time constraints and requireflexible, predictable, and fast reactive handling of incoming events. However,RISC- V processors are still lagging in this area compared to more matureproprietary architectures, such as ARM Cortex-M and TriCore, which have beentuned for years. The default interrupt controller standardized by RISC-V, theCore Local Interruptor (CLINT), lacks configurability in prioritization andpreemption of interrupts. The RISC-V Core Local Interrupt Controller (CLIC)specification addresses this concern by enabling pre-emptible, low-latencyvectored interrupts while also envisioning optional extensions to improveinterrupt latency. In this work, we implement a CLIC for the CV32E40P, anindustrially supported open-source 32-bit MCU-class RISC-V core, and enhance itwith fastirq: a custom extension that provides interrupt latency as low as 6cycles. We call CV32RT our enhanced core. To the best of our knowledge, CV32RTis the first fully open-source RV32 core with competitive interrupt-handlingfeatures compared to the Arm Cortex-M series and TriCore. The proposedextensions are also demonstrated to improve task context switching in real-timeoperating systems.

CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers