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Factorization and multiplication of dense matrices and tensors are critical,yet extremely expensive pieces of the scientific toolbox. Careful use of lowrank approximation can drastically reduce the computation and memoryrequirements of these operations. In addition to a lower arithmetic complexity,such methods can, by their structure, be designed to efficiently exploit modernhardware architectures. The majority of existing work relies on batched BLASlibraries to handle the computation of many small dense matrices. We show thatthrough careful analysis of the cache utilization, register accumulation usingSIMD registers and a redesign of the implementation, one can achievesignificantly higher throughput for these types of batched low-rank matricesacross a large range of block and batch sizes. We test our algorithm on 3 CPUsusing diverse ISAs -- the Fujitsu A64FX using ARM SVE, the Intel Xeon 6148using AVX-512 and AMD EPYC 7502 using AVX-2, and show that our new batchingmethodology is able to obtain more than twice the throughput of vendoroptimized libraries for all CPU architectures and problem sizes.

Cache Optimization and Performance Modeling of Batched, Small, and Rectangular Matrix Multiplication on Intel, AMD, and Fujitsu Processors