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As the complexity of System-on-Chip (SoC) designs continues to increase,ensuring thorough verification becomes a significant challenge for systemintegrators. The complexity of verification can result in undetected bugs.Unlike software or firmware bugs, hardware bugs are hard to fix afterdeployment and they require additional logic, i.e., patching logic integratedwith the design in advance in order to patch. However, the absence of astandardized metric for defining "patchability" leaves system integratorsrelying on their understanding of each IP and security requirements to engineerad hoc patching designs. In this paper, we propose a theoretical patchabilityquantification method to analyze designs at the Register Transfer Level (RTL)with provided patching options. Our quantification defines patchability as acombination of observability and controllability so that we can analyze andcompare the patchability of IP variations. This quantification is a systematicapproach to estimate each patching architecture's ability to patch at run-timeand complements existing patching works. In experiments, we compare severaldesign options of the same patching architecture and discuss their differencesin terms of theoretical patchability and how many potential weaknesses can bemitigated.

Theoretical Patchability Quantification for IP-Level Hardware Patching Designs