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This work reports the performance evaluation of an SDR readout system basedon the latest generation (Gen3) of the AMD's Radio Frequency System-on-Chip(RFSoC) processing platform, which integrates a full-stack processing systemand a powerful FPGA with up to 32 high-speed and high-resolution 14-bitDigital-to-Analog Converters (DACs) and Analog-to-Digital Converters (ADCs).The proposed readout system uses a previously developed multi-band,double-conversion IQ RF-mixing board targeting a multiplexing factor ofapproximately 1,000 bolometers in a bandwidth between 4 and 8 GHz, in line withstate-of-the-art microwave SQUID multiplexers ($\mu$MUX). The characterizationof the system was performed in two stages, under the conditions typicallyimposed by the multiplexer and the cold readout circuit. First, intransmission, showing that noise and spurious levels of the generated tones areclose to the values imposed by the cold readout. Second, in RF loopback,presenting noise values better than -100 dBc/Hz totally in agreement with thestate-of-the-art readout systems. It was demonstrated that the RFSoC Gen3device is a suitable enabling technology for the next generation ofsuperconducting detector readout systems, reducing system complexity,increasing system integration, and achieving these goals without performancedegradation.

RFSoC Gen3-Based Software-Defined Radio Characterization for the Readout System of Low-Temperature Bolometers