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Accelerating Human Action Recognition (HAR) efficiently for real-timesurveillance and robotic systems on edge chips remains a challenging researchfield, given its high computational and memory requirements. This paperproposed an integrated end-to-end HAR scalable HW/SW accelerator co-designbased on an enhanced 8-bit quantized Two-Stream SimpleNet-PyTorch CNNarchitecture. Our network accelerator was trained on UCF101 and UCF24 datasetsand implemented on edge SoC-FPGA. Our development uses partially streamingdataflow architecture to achieve higher throughput versus network design andresource utilization trade-off. We also fused all convolutional, batch-norm,and ReLU operations into a single homogeneous layer and utilized theLucas-Kanade motion flow method to enable a high parallelism accelerator designand optimized on-chip engine computing.Furthermore, our proposed methodologyachieved nearly 81% prediction accuracy with an approximately 24 FPS real-timeinference throughput at 187MHz on ZCU104, which is 1.7x - 1.9x higher than theprior research. Lastly, the designed framework was benchmarked against severalhardware chips for higher throughput and performance measurements and is nowavailable as an open-source project on GitHub for training and implementationon edge platforms.

FPGA-QHAR: Throughput-Optimized for Quantized Human Action Recognition on The Edge