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The high volume of data transmission between the edge sensor and the cloudprocessor leads to energy and throughput bottlenecks for resource-constrainededge devices focused on computer vision. Hence, researchers are investigatingdifferent approaches (e.g., near-sensor processing, in-sensor processing,in-pixel processing) by executing computations closer to the sensor to reducethe transmission bandwidth. Specifically, in-pixel processing for neuromorphicvision sensors (e.g., dynamic vision sensors (DVS)) involves incorporatingasynchronous multiply-accumulate (MAC) operations within the pixel array,resulting in improved energy efficiency. In a CMOS implementation, low overheadenergy-efficient analog MAC accumulates charges on a passive capacitor;however, the capacitor's limited charge retention time affects the algorithmicintegration time choices, impacting the algorithmic accuracy, bandwidth,energy, and training efficiency. Consequently, this results in a designtrade-off on the hardware aspect-creating a need for a low-leakage compute unitwhile maintaining the area and energy benefits. In this work, we present aholistic analysis of the hardware-algorithm co-design trade-off based on thelimited integration time posed by the hardware and techniques to improve theleakage performance of the in-pixel analog MAC operations.

Hardware-Algorithm Co-design Enabling Processing-in-Pixel-in-Memory (P2M) for Neuromorphic Vision Sensors