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Recognizing the explosive increase in the use of DNN-based applications,several industrial companies developed a custom ASIC (e.g., Google TPU, IBMRaPiD, Intel NNP-I/NNP-T) and constructed a hyperscale cloud infrastructurewith it. The ASIC performs operations of the inference or training process ofDNN models which are requested by users. Since the DNN models have differentdata formats and types of operations, the ASIC needs to support diverse dataformats and generality for the operations. However, the conventional ASICs donot fulfill these requirements. To overcome the limitations of it, we propose aflexible DNN accelerator called All-rounder. The accelerator is designed withan area-efficient multiplier supporting multiple precisions of integer andfloating point datatypes. In addition, it constitutes a flexibly fusible andfissionable MAC array to support various types of DNN operations efficiently.We implemented the register transfer level (RTL) design using Verilog andsynthesized it in 28nm CMOS technology. To examine practical effectiveness ofour proposed designs, we designed two multiply units and three state-of-the-artDNN accelerators. We compare our multiplier with the multiply units and performarchitectural evaluation on performance and energy efficiency with eightreal-world DNN models. Furthermore, we compare benefits of the All-rounderaccelerator to a high-end GPU card, i.e., NVIDIA GeForce RTX30390. The proposedAll-rounder accelerator universally has speedup and high energy efficiency invarious DNN benchmarks than the baselines.

All-rounder: A flexible DNN accelerator with diverse data format support