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Post-layout simulation provides accurate guidance for analog circuit design,but post-layout performance is hard to be directly optimized at early designstages. Prior work on analog circuit sizing often utilizes pre-layoutsimulation results as the optimization objective. In this work, we propose apost-layout-simulation-driven (post-simulation-driven for short) analog circuitsizing framework that directly optimizes the post-layout simulationperformance. The framework integrates automated layout generation into theoptimization loop of transistor sizing and leverages a coupled Bayesianoptimization algorithm to search for the best post-simulation performance.Experimental results demonstrate that our framework can achieve over 20% betterpost-layout performance in competitive time than manual design and the methodthat only considers pre-layout optimization.

Post-Layout Simulation Driven Analog Circuit Sizing