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Resistive random access memory (ReRAM)-based processing-in-memory (PIM)architectures have demonstrated great potential to accelerate Deep NeuralNetwork (DNN) training/inference. However, the computational accuracy of analogPIM is compromised due to the non-idealities, such as the conductance variationof ReRAM cells. The impact of these non-idealities worsens as the number ofconcurrently activated wordlines and bitlines increases. To guaranteecomputational accuracy, only a limited number of wordlines and bitlines of thecrossbar array can be turned on concurrently, significantly reducing theachievable parallelism of the architecture.  While the constraints on parallelism limit the efficiency of theaccelerators, they also provide a new opportunity for fine-grainedmixed-precision quantization. To enable efficient DNN inference on practicalReRAM-based accelerators, we propose an algorithm-architecture co-designframework called \underline{B}lock-\underline{W}ise mixed-precision\underline{Q}uantization (BWQ). At the algorithm level, BWQ-A introduces amixed-precision quantization scheme at the block level, which achieves a highweight and activation compression ratio with negligible accuracy degradation.We also present the hardware architecture design BWQ-H, which leverages thelow-bit-width models achieved by BWQ-A to perform high-efficiency DNN inferenceon ReRAM devices. BWQ-H also adopts a novel precision-aware weight mappingmethod to increase the ReRAM crossbar's throughput. Our evaluation demonstratesthe effectiveness of BWQ, which achieves a 6.08x speedup and a 17.47x energysaving on average compared to existing ReRAM-based architectures.

Block-Wise Mixed-Precision Quantization: Enabling High Efficiency for Practical ReRAM-based DNN Accelerators