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Spectral-domain CNNs have been shown to be more efficient than traditionalspatial CNNs in terms of reducing computation complexity. However they comewith a `kernel explosion' problem that, even after compression (pruning),imposes a high memory burden and off-chip bandwidth requirement for kernelaccess. This creates a performance gap between the potential accelerationoffered by compression and actual FPGA implementation performance, especiallyfor low-latency CNN inference. In this paper, we develop a principled approachto overcoming this performance gap and designing a low-latency, low-bandwidth,spectral sparse CNN accelerator on FPGAs. First, we analyze thebandwidth-storage tradeoff of sparse convolutional layers and locatecommunication bottlenecks. We then develop a dataflow for flexibly optimizingdata reuse in different layers to minimize off-chip communication. Finally, wepropose a novel scheduling algorithm to optimally schedule the on-chip memoryaccess of multiple sparse kernels and minimize read conflicts. On astate-of-the-art FPGA platform, our design reduces data transfers by 42\% withDSP utilization up to 90\% and achieves inference latency of 9 ms for VGG16,compared to the baseline state-of-the-art latency of 68 ms.

Reuse Kernels or Activations? A Flexible Dataflow for Low-latency Spectral CNN Acceleration