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Time-Aware Shaper (TAS) is a time-triggered scheduling mechanism that ensuresbounded latency for time-critical Scheduled Traffic (ST) flows. The Linuxkernel implementation (a.k.a TAPRIO) has limited capabilities due to varyingCPU workloads and thus does not offer tight latency bound for the ST flows.Also, currently only higher cycle times are possible. Other softwareimplementations are limited to simulation studies without physicalimplementation. In this paper, we present $\mu$TAS, a MicroC-based hardwareimplementation of TAS onto a programmable SmartNIC. $\mu$TAS takes advantage ofthe parallel-processing architecture of the SmartNIC to configure thescheduling behaviour of its queues at runtime. To demonstrate the effectivenessof $\mu$TAS, we built a Time-Sensitive Networking (TSN) testbed from scratch.This consists of multiple end-hosts capable of generating ST and Best Effort(BE) flows and TSN switches equipped with SmartNICs running $\mu$TAS. Timesynchronization is maintained between the switches and hosts. Our experimentsdemonstrate that the ST flows experience a bounded latency of the order of tensof microseconds.

$\mu$TAS: Design and implementation of Time Aware Shaper on SmartNICs to achieve bounded latency