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HQC is one of the code-based finalists in the last round of the NIST postquantum cryptography standardization process. In this process, security andimplementation efficiency are key metrics for the selection of the candidates.A critical compute kernel with respect to efficient hardware implementationsand security in HQC is the sampling method used to derive random numbers. Dueto its security criticality, recently an updated sampling algorithm waspresented to increase its robustness against side-channel attacks.  In this paper, we pursue a cross layer approach to optimize this new samplingalgorithm to enable an efficient hardware implementation without comprising theoriginal algorithmic security and side-channel attack robustness.  We compare our cross layer based implementation to a direct hardwareimplementation of the original algorithm and to optimized implementations ofthe previous sampler version. All implementations are evaluated using theXilinx Artix 7 FPGA. Our results show that our approach reduces the latency bya factor of 24 compared to the original algorithm and by a factor of 28compared to the previously used sampler with significantly less resources.

Efficient Hardware Implementation of Constant Time Sampling for HQC