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Residual neural networks are widely used in computer vision tasks. Theyenable the construction of deeper and more accurate models by mitigating thevanishing gradient problem. Their main innovation is the residual block whichallows the output of one layer to bypass one or more intermediate layers and beadded to the output of a later layer. Their complex structure and the bufferingrequired by the residual block make them difficult to implement onresource-constrained platforms. We present a novel design flow for implementingdeep learning models for field programmable gate arrays optimized for ResNets,using a strategy to reduce their buffering overhead to obtain aresource-efficient implementation of the residual layer. Our high-levelsynthesis (HLS)-based flow encompasses a thorough set of design principles andoptimization strategies, exploiting in novel ways standard techniques such astemporal reuse and loop merging to efficiently map ResNet models, andpotentially other skip connection-based NN architectures, into FPGA. The modelsare quantized to 8-bit integers for both weights and activations, 16-bit forbiases, and 32-bit for accumulations. The experimental results are obtained onthe CIFAR-10 dataset using ResNet8 and ResNet20 implemented with Xilinx FPGAsusing HLS on the Ultra96-V2 and Kria KV260 boards. Compared to thestate-of-the-art on the Kria KV260 board, our ResNet20 implementation achieves2.88X speedup with 0.5% higher accuracy of 91.3%, while ResNet8 accuracyimproves by 2.8% to 88.7%. The throughputs of ResNet8 and ResNet20 are 12971FPS and 3254 FPS on the Ultra96 board, and 30153 FPS and 7601 FPS on the KriaKV26, respectively. They Pareto-dominate state-of-the-art solutions concerningaccuracy, throughput, and energy.

Design and Optimization of Residual Neural Network Accelerators for Low-Power FPGAs Using High-Level Synthesis