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Microarchitectural timing side channels have been thoroughly investigated asa security threat in hardware designs featuring shared buffers (e.g., caches)and/or parallelism between attacker and victim task execution. Contradictingcommon intuitions, recent activities demonstrate, however, that this threat isreal also in microcontroller SoCs without such features. In this paper, wedescribe SoC-wide timing side channels previously neglected by securityanalysis and present a new formal method to close this gap. In a case studywith the RISC-V Pulpissimo SoC platform, our method found a vulnerability to aso far unknown attack variant that allows an attacker to obtain informationabout a victim's memory access behavior. After implementing a conservative fix,we were able to verify that the SoC is now secure w.r.t. timing side channels.

A New Security Threat in MCUs -- SoC-wide timing side channels and how to find them