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Memory interference may heavily inflate task execution times in HeterogeneousSystems-on-Chips (HeSoCs). Knowing worst-case interference is consequentlyfundamental for supporting the correct execution of time-sensitiveapplications. In most of the literature, worst-case interference is assumed tobe generated by, and therefore is estimated through read-intensive syntheticworkloads with no caching. Yet these workloads do not always generateworst-case interference. This is the consequence of the general resultsreported in this work. By testing on multiple architectures, we determined thatthe highest interference generation traffic pattern is actually hardwaredependant, and that making assumptions could lead to a severe underestimationof the worst-case (in our case, of more than 9x).

The Importance of Worst-Case Memory Contention Analysis for Heterogeneous SoCs