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The ever-increasing computational and storage requirements of modernapplications and the slowdown of technology scaling pose major challenges todesigning and implementing efficient computer architectures. In this paper, weleverage the architectural balance principle to alleviate the bandwidthbottleneck at the L1 data memory boundary of a tightly-coupled cluster ofprocessing elements (PEs). We thus explore coupling each PE with an L0 memory,namely a private register file implemented as Standard Cell Memory (SCM).Architecturally, the SCM is the Vector Register File (VRF) of Spatz, a compact64-bit floating-point-capable vector processor based on RISC-V's VectorExtension Zve64d. Unlike typical vector processors, whose VRF are hundreds ofKiB large, we prove that Spatz can achieve peak energy efficiency with a VRF ofonly 2 KiB. An implementation of the Spatz-based cluster in GlobalFoundries'12LPP process with eight double-precision Floating Point Units (FPUs) achievesan FPU utilization just 3.4% lower than the ideal upper bound on adouble-precision, floating-point matrix multiplication. The cluster reaches 7.7FMA/cycle, corresponding to 15.7 GFLOPS-DP and 95.7 GFLOPS-DP/W at 1 GHz andnominal operating conditions (TT, 0.80V, 25^oC) with more than 55% of the powerspent on the FPUs. Furthermore, the optimally-balanced Spatz-based clusterreaches a 95.0% FPU utilization (7.6 FMA/cycle), 15.2 GFLOPS-DP, and 99.3GFLOPS-DP/W (61% of the power spent in the FPU) on a 2D workload with a 7x7kernel, resulting in an outstanding area/energy efficiency of 171GFLOPS-DP/W/mm^2. At equi-area, our computing cluster built upon compact vectorprocessors reaches a 30% higher energy efficiency than a cluster with the sameFPU count built upon scalar cores specialized for stream-based floating-pointcomputation.

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency