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We propose a Digit-Serial Left-tO-righT (DSLOT) arithmetic based processingtechnique called DSLOT-NN with aim to accelerate inference of the convolutionoperation in the deep neural networks (DNNs). The proposed work has the abilityto assess and terminate the ineffective convolutions which results in massivepower and energy savings. The processing engine is comprised of low-latencymost-significant-digit-first (MSDF) (also called online) multipliers and addersthat processes data from left-to-right, allowing the execution of subsequentoperations in digit-pipelined manner. Use of online operators eliminates theneed for the development of complex mechanism of identifying the negativeactivation, as the output with highest weight value is generated first, and thesign of the result can be identified as soon as first non-zero digit isgenerated. The precision of the online operators can be tuned at run-time,making them extremely useful in situations where accuracy can be compromisedfor power and energy savings. The proposed design has been implemented onXilinx Virtex-7 FPGA and is compared with state-of-the-art Stripes on variousperformance metrics. The results show the proposed design presents powersavings, has shorter cycle time, and approximately 50% higher OPS per watt.

DSLOT-NN: Digit-Serial Left-to-Right Neural Network Accelerator