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CXL has been the emerging technology for expanding memory for both the hostCPU and device accelerators with load/store interface. Extending memorycoherency to the PCIe root complex makes the codesign more flexible in that youcan access the memory with coherency using your near-device computability.Since the capacity demand with tolerable latency and bandwidth is growing, weneed to come up with a new hardware-software codesign way to offload thesynthesized memory operations to the CXL endpoint, CXL switch or near CXL rootcomplex cores like Intel DSA to fetch data; the CPU or accelerators cancalculate other stuff in the backend. On CXL done loading, the data will be putinto L1 if capacity fits, and the in-core ROB will be notified by mailbox andresume the calculation on the previous hardware context. Since thedistance(timing window) of the load instruction sequence is unknown, aprofiling-guided way of codegening and adaptively updating offloaded code willbe required for a long-running job. We propose to evaluate CXLMemUring themodified BOOMv3 with added in-core-logic and CXL endpoint access simulationusing CHI, and we will add a weaker RISCV Core near endpoint for codeoffloading, and the codegening will be based on program analysis withtraditional profiling guided way.

CXLMemUring: A Hardware Software Co-design Paradigm for Asynchronous and Flexible Parallel CXL Memory Pool Access