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RRAM-based multi-core systems improve the energy efficiency and performanceof CNNs. Thereby, the distributed parallel execution of convolutional layerscauses critical data dependencies that limit the potential speedup. This paperpresents synchronization techniques for parallel inference of convolutionallayers on RRAM-based CIM architectures. We propose an architecture optimizationthat enables efficient data exchange and discuss the impact of differentarchitecture setups on the performance. The corresponding compiler algorithmsare optimized for high speedup and low memory consumption during CNN inference.We achieve more than 99% of the theoretical acceleration limit with a marginaldata transmission overhead of less than 4% for state-of-the-art CNN benchmarks.

Mapping of CNNs on multi-core RRAM-based CIM architectures