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Fast binary compressors are the main components of many basic digitalcalculation units. In this paper, a high-speed (7,2) compressor with a fastcarry-generation logic is proposed. The carry-generation logic is based on thesorting network, and it can generate a carry bit within 2 logical stages otherthan 3 stages as in previous school book full adders. Collaborating with theadjusted full adder logic, the proposed (7,2) compressor achieves using only 11basic logical stages. Testing this new design in a binary arry with 7 rows and8 columns, and the result shows that this design have higher proformance thanprevious designs. This method is suitable for high proformance cases inmultiplication design or other cryptography hardware blocks.

High-Speed (7,2) Compressor Using A Fast Carry-Generation Logic based on Sorting Network