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With the rapid advancements of deep learning in recent years, hardwareaccelerators are continuously deployed in more and more safety-criticalapplications such as autonomous driving and robotics. While the acceleratorsare usually fabricated with advanced technology nodes for high performance andenergy efficiency, they are also more prone to timing errors under process,voltage, temperature, and aging (PVTA) variations. By revisiting the physicalsources of timing errors, we show that most of the timing errors in theaccelerator are caused by a specific subset of input patterns, defined ascritical input patterns. To improve the timing error resilience of theaccelerator, in this paper, we propose READ, a reliability-enhanced acceleratordataflow optimization technique that can effectively reduce timing errors. READreduces the occurrence of critical input patterns by exploring the optimalcomputing sequence when mapping a trained deep neural network to accelerators.READ only changes the order of multiply-accumulate operations in a convolution,which introduces negligible hardware overhead and no impact on accuracy. Theexperimental results on VGG and ResNet demonstrate on average 7.8X timing errorrate (TER) reduction and up to 37.9X TER reduction for certain layers. Theresults also show that READ enables the accelerator to maintain accuracy over awide range of PVTA variations, making it a promising approach for robustdeep-learning design

READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction