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Turbo-Codes (TC) are a family of convolutional codes enablingForward-Error-Correction (FEC) while approaching the theoretical limit ofchannel capacity predicted by Shannons theorem. One of the bottlenecks of aTurbo Encoder (TE) lies in the non-uniform interleaving stage. Interleavingalgorithms require stalling the input vector bits before the bit rearrangementcausing a delay in the overall process. This paper presents performanceenhancement via a parallel algorithm for the interleaving stage of a TurboEncoder application compliant with the DVB-RCS2 standard. The algorithmefficiently implements the interleaving operation while utilizing attributes ofa given DSP. We will discuss and compare a serial model for the TE, with thepresented parallel processed algorithm. Results showed a speed-up factor of upto 3.4 Total-Cycles, 4.8 Write and 7.3 Read.

A Novel Reconfigurable Vector-Processed Interleaving Algorithm for a DVB-RCS2 Turbo Encoder