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Gate-all-around (GAA) nanowire (NW) field-effect transistor (FET) is apromising device architecture due to its superior gate controllability thanthat of the conventional FinFET architecture. The significantly higher electronmobility of indium phosphide (InP) NW than silicon NW makes it particularlywell-suited for high-performance (HP) electronics applications. In this work,we perform an ab initio quantum transport simulation to investigate theperformance limit of sub-5-nm gate length (Lg) GAA InP NW FETs. The GAA InP NWFETs with Lg of 4 nm can meet the International Technology Roadmap forSemiconductors (ITRS) requirements for HP devices from the perspective ofon-state current, delay time, and power dissipation. We also investigate theimpact of strain on 3-nm-Lg GAA InP NW FETs. The application of tensile strainresults in a remarkable increase of over 60% in the on-state current. Theseresults highlight the potential of GAA InP NW FETs for HP applications in thesub-5-nm Lg region.

Sub-5 nm Gate-All-Around InP Nanowire Transistors Towards High-Performance Devices