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We develop a hardware-efficient ansatz for variational optimization, derivedfrom existing ansatze in the literature, that parametrizes subsets of allinteractions in the Cost Hamiltonian in each layer. We treat gate orderings asa variational parameter and observe that doing so can provide significantperformance boosts in experiments. We carried out experimental runs of acompilation-optimized implementation of fully-connected Sherrington-KirkpatrickHamiltonians on a 50-qubit linear-chain subsystem of Rigetti Aspen-M-3 transmonprocessor. Our results indicate that, for the best circuit designs tested, theaverage performance at optimized angles and gate orderings increases withcircuit depth (using more parameters), despite the presence of a high level ofnoise. We report performance significantly better than using a random guessoracle for circuits involving up to approx 5000 two-qubit and approx 5000one-qubit native gates. We additionally discuss various takeaways of ourresults toward more effective utilization of current and future quantumprocessors for optimization.

Design and execution of quantum circuits using tens of superconducting qubits and thousands of gates for dense Ising optimization problems