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We propose a novel constrained Bayesian Optimization (BO) algorithmoptimizing the design process of Laterally-Diffused Metal-Oxide-Semiconductor(LDMOS) transistors while realizing a target Breakdown Voltage (BV). We convertthe constrained BO problem into a conventional BO problem using a Lagrangemultiplier. Instead of directly optimizing the traditional Figure-of-Merit(FOM), we set the Lagrangian as the objective function of BO. This adaptiveobjective function with a changeable Lagrange multiplier can addressconstrained BO problems which have constraints that require costly evaluations,without the need for additional surrogate models to approximate constraints.Our algorithm enables a device designer to set the target BV in the designspace, and obtain a device that satisfies the optimized FOM and the target BVconstraint automatically. Utilizing this algorithm, we have also explored thephysical limits of the FOM for our devices in 30 - 50 V range within thedefined design space.

Constrained Bayesian Optimization Using a Lagrange Multiplier Applied to Power Transistor Design