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High-level synthesis (HLS) is a process that automatically translates asoftware program in a high-level language into a low-level hardwaredescription. However, the hardware designs produced by HLS tools still sufferfrom a significant performance gap compared to manual implementations. This isbecause the input HLS programs must still be written using hardware designprinciples.  Existing techniques either leave the program source unchanged or perform afixed sequence of source transformation passes, potentially missingopportunities to find the optimal design. We propose a super-optimizationapproach for HLS that automatically rewrites an arbitrary software program intoefficient HLS code that can be used to generate an optimized hardware design.We developed a toolflow named SEER, based on the e-graph data structure, toefficiently explore equivalent implementations of a program at scale. SEERprovides an extensible framework, orchestrating existing software compilerpasses and hardware synthesis optimizers.  Our work is the first attempt to exploit e-graph rewriting for large softwarecompiler frameworks, such as MLIR. Across a set of open-source benchmarks, weshow that SEER achieves up to 38x the performance within 1.4x the area of theoriginal program. Via an Intel-provided case study, SEER demonstrates thepotential to outperform manually optimized designs produced by hardwareexperts.

SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR