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In this article, we introduce an instruction set architecture (ISA) forprocessing-in-memory (PIM) based deep neural network (DNN) accelerators. Theproposed ISA is for DNN inference on PIM-based architectures. It is assumedthat the weights have been trained and programmed into PIM-based DNNaccelerators before inference, and they are fixed during inference. We do notrestrict the devices of PIM-based DNN accelerators. Popular devices used tobuild PIM-based DNN accelerators include resistive random-access memory (RRAM),flash, ferroelectric field-effect transistor (FeFET), static random-accessmemory (SRAM), etc. The target DNNs include convolutional neural networks(CNNs) and multi-layer perceptrons (MLPs). The proposed ISA is transparent toboth applications and hardware implementations. It enables to develop unifiedtoolchains for PIM-based DNN accelerators and software stacks. For practicalhardware that uses a different ISA, the generated instructions by unifiedtoolchains can easily converted to the target ISA. The proposed ISA has beenused in the open-source DNN compiler PIMCOMP-NN(https://github.com/sunxt99/PIMCOMP-NN) and the associated open-sourcesimulator PIMSIM-NN (https://github.com/wangxy-2000/pimsim-nn).

Instruction Set Architecture (ISA) for Processing-in-Memory DNN Accelerators