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An increasing number of researchers are finding use for nth-order gradientcomputations for a wide variety of applications, including graphics,meta-learning (MAML), scientific computing, and most recently, implicit neuralrepresentations (INRs). Recent work shows that the gradient of an INR can beused to edit the data it represents directly without needing to convert it backto a discrete representation. However, given a function represented as acomputation graph, traditional architectures face challenges in efficientlycomputing its nth-order gradient due to the higher demand for computing powerand higher complexity in data movement. This makes it a promising target forFPGA acceleration. In this work, we introduce INR-Arch, a framework thattransforms the computation graph of an nth-order gradient into ahardware-optimized dataflow architecture. We address this problem in twophases. First, we design a dataflow architecture that uses FIFO streams and anoptimized computation kernel library, ensuring high memory efficiency andparallel computation. Second, we propose a compiler that extracts and optimizescomputation graphs, automatically configures hardware parameters such aslatency and stream depths to optimize throughput, while ensuring deadlock-freeoperation, and outputs High-Level Synthesis (HLS) code for FPGA implementation.We utilize INR editing as our benchmark, presenting results that demonstrate1.8-4.8x and 1.5-3.6x speedup compared to CPU and GPU baselines respectively.Furthermore, we obtain 3.1-8.9x and 1.7-4.3x lower memory usage, and 1.7-11.3xand 5.5-32.8x lower energy-delay product. Our framework will be madeopen-source and available on GitHub.

INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation Processing