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Fully homomorphic encryption (FHE) is in the spotlight as a definitivesolution for privacy, but the high computational overhead of FHE poses achallenge to its practical adoption. Although prior studies have attempted todesign ASIC accelerators to mitigate the overhead, their designs requireexcessive amounts of chip resources (e.g., areas) to contain and processmassive data for FHE operations.  We propose CiFHER, a chiplet-based FHE accelerator with a resizablestructure, to tackle the challenge with a cost-effective multi-chip module(MCM) design. First, we devise a flexible architecture of a chiplet core whoseconfiguration can be adjusted to conform to the global organization of chipletsand design constraints. The distinctive feature of our core is a recomposablefunctional unit providing varying computational throughput for number-theoretictransform (NTT), the most dominant function in FHE. Then, we establishgeneralized data mapping methodologies to minimize the network overhead whenorganizing the chips into the MCM package in a tiled manner, which becomes asignificant bottleneck due to the technology constraints of MCMs. Also, weanalyze the effectiveness of various algorithms, including a novel limbduplication algorithm, on the MCM architecture. A detailed evaluation showsthat a CiFHER package composed of 4 to 64 compact chiplets provides performancecomparable to state-of-the-art monolithic ASIC FHE accelerators withsignificantly lower package-wide power consumption while reducing the area of asingle core to as small as 4.28mm$^2$.

CiFHER: A Chiplet-Based FHE Accelerator with a Resizable Structure