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Hardware implementations of Spiking Neural Networks (SNNs) represent apromising approach to edge-computing for applications that require low-powerand low-latency, and which cannot resort to external cloud-based computingservices. However, most solutions proposed so far either support onlyrelatively small networks, or take up significant hardware resources, toimplement large networks. To realize large-scale and scalable SNNs it isnecessary to develop an efficient asynchronous communication and routing fabricthat enables the design of multi-core architectures. In particular the coreinterface that manages inter-core spike communication is a crucial component asit represents the bottleneck of Power-Performance-Area (PPA) especially for thearbitration architecture and the routing memory. In this paper we present anarbitration mechanism with the corresponding asynchronous encoding pipelinecircuits, based on hierarchical arbiter trees. The proposed scheme reduces thelatency by more than 70% in sparse-event mode, compared to the state-of-the-artarbitration architectures, with lower area cost. The routing memory makes useof asynchronous Content Addressable Memory (CAM) with Current SensingCompletion Detection (CSCD), which saves approximately 46% energy, and achievesa 40% increase in throughput against conventional asynchronous CAM usingconfigurable delay lines, at the cost of only a slight increase in area. Inaddition as it radically reduces the core interface resources in multi-coreneuromorphic processors, the arbitration architecture and CAM architecture wepropose can be also applied to a wide range of general asynchronous circuitsand systems.

Core interface optimization for multi-core neuromorphic processors