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Modeling system-level behaviors of intricate System-on-Chip (SoC) designs iscrucial for design analysis, testing, and validation. However, the complexityand volume of SoC traces pose significant challenges in this task. This paperproposes an approach to automatically infer concise and abstract models fromSoC communication traces, capturing the system-level protocols that governmessage exchange and coordination between design blocks for various systemfunctions. This approach, referred to as model synthesis, constructs acausality graph with annotations obtained from the SoC traces. The annotatedcausality graph represents all potential causality relations among messagesunder consideration. Next, a constraint satisfaction problem is formulated fromthe causality graph, which is then solved by a satisfiability modulo theories(SMT) solver to find satisfying solutions. Finally, finite state models areextracted from the generated solutions, which can be used to explain andunderstand the input traces. The proposed approach is validated throughexperiments using synthetic traces obtained from simulating a transaction-levelmodel of a multicore SoC design and traces collected from running real programson a realistic multicore SoC modeled with gem5.

AutoModel: Automatic Synthesis of Models from Communication Traces of SoC Designs