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Multi-die FPGAs are crucial components in modern computing systems,particularly for high-performance applications such as artificial intelligenceand data centers. Super long lines (SLLs) provide interconnections betweensuper logic regions (SLRs) for a multi-die FPGA on a silicon interposer. Theyhave significantly higher delay compared to regular interconnects, which needto be minimized. With the increase in design complexity, the growth of SLLsgives rise to challenges in timing and power closure. Existing placementalgorithms focus on optimizing the number of SLLs but often face limitationsdue to specific topologies of SLRs. Furthermore, they fall short of achievingcontinuous optimization of SLLs throughout the entire placement process. Thishighlights the necessity for more advanced and adaptable solutions.  In this paper, we propose LEAPS, a comprehensive, systematic, and adaptablemulti-die FPGA placement algorithm for SLL minimization. Our contributions arethreefold: 1) proposing a high-performance global placement algorithm formulti-die FPGAs that optimizes the number of SLLs while addressing otheressential design constraints such as wirelength, routability, and clockrouting; 2) introducing a versatile method for more complex SLR topologies ofmulti-die FPGAs, surpassing the limitations of existing approaches; and 3)executing continuous optimization of SLLs across the whole placement stages,including global placement (GP), legalization (LG), and detailed placement(DP). Experimental results demonstrate the effectiveness of LEAPS in reducingSLLs and enhancing circuit performance. Compared with the most recentstate-of-the-art (SOTA) method, LEAPS achieves an average reduction of 40.19%in SLLs and 9.99% in HPWL, while exhibiting a notable 34.34$\times$ improvementin runtime.

LEAPS: Topological-Layout-Adaptable Multi-die FPGA Placement for Super Long Line Minimization