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The globalization of semiconductor supply chains has exposed Network-on-Chip(NoC) interconnects in System-on-Chip (SoC) architectures to critical securityrisks, including reverse engineering and IP theft. To address these threats,this work builds on two methodologies: ObNoCs [11], which obfuscates NoCtopologies using programmable multiplexers, and POTENT [10], which enhancespost-synthesis security against SAT-based attacks. These techniques ensurerobust protection of NoC interconnects with minimal performance overhead. Asthe industry shifts to chiplet-based heterogeneous architectures, this researchextends ObNoCs and POTENT to secure intra- and inter-chiplet interconnects. Newchallenges, such as safeguarding inter-chiplet communication and interposerdesign, are addressed through enhanced obfuscation, authentication, andencryption mechanisms. Experimental results demonstrate the practicality ofthese approaches for high-security applications, ensuring trust and reliabilityin monolithic and modular systems.

Designing Secure Interconnects for Modern Microelectronics: From SoCs to Emerging Chiplet-Based Architectures