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The various benefits of multi-tenanting, such as higher device utilizationand increased profit margin, intrigue the cloud field-programmable gate array(FPGA) servers to include multi-tenanting in their infrastructure. However,this property makes these servers vulnerable to power side-channel (PSC)attacks. Logic designs such as ring oscillator (RO) and time-to-digitalconverter (TDC) are used to measure the power consumed by security criticalcircuits, such as advanced encryption standard (AES). Firstly, the existingworks require higher minimum traces for disclosure (MTD). Hence, in this work,we improve the sensitivity of the TDC-based sensors by manually placing theFPGA primitives inferring these sensors. This enhancement helps to determinethe 128-bit AES key using 3.8K traces. Secondly, the existing defenses use ROsto defend against PSC attacks. However, cloud servers such as Amazon WebServices (AWS) block design with combinatorial loops. Hence, we propose aplacement-based defense. We study the impact of (i) primitive-level placementon the AES design and (ii) additional logic that resides along with the AES onthe correlation power analysis (CPA) attack results. Our results showcase thatthe AES along with filters and/or processors are sufficient to provide the samelevel or better security than the existing defenses.

Securing Cloud FPGAs Against Power Side-Channel Attacks: A Case Study on Iterative AES