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Monolithic 3D integration has become a promising solution for futurecomputing needs. The metal inter-layer via (MIV) forms interconnects betweensubstrate layers in Monolithic 3D integration. Despite small size of MIV, thearea overhead can become a major limitation for efficient M3D integration and,thus needs to be addressed. Previous works focused on the utilization of thesubstrate area around MIV to reduce this area overhead significantly butsuffers from increased leakage and scaling factors. In this work, we discussMIV-transistor realization that addresses both leakage and scaling issue alongwith similar area overhead reduction compared with previous works and, thus canbe utilized efficiently. Our simulation results suggest that the leakagecurrent $(I_{D,leak})$ has reduced by $14K\times$ and, the maximum current$(I_{D,max})$ increased by $58\%$ for the proposed MIV-transistor compared withthe previous implementation. In addition, performance metrics of the inverterrealization with our proposed MIV-transistor specifically the delay, slew timeand power consumption reduced by $11.6\%$, $17.9\%$ and, $4.5\%$ respectivelycompared with the previous implementation with same MIV area overheadreduction.

Efficient and Scalable MIV-transistor with Extended Gate in Monolithic 3D Integration