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Monolithic Three-Dimensional Integrated Circuits (M3D-IC) has become anattractive option to increase the transistor density. In M3D-IC, substratelayers are realized on top of previous layers using sequential integrationtechniques. Recent works in M3D-IC have demonstrated the feasibility of FDSOIprocess-based M3D-IC implementations and, Metal inter-layer vias (MIVs) areused to provide connections between the inter-layer devices. Since MIVs areextended from bottom layer to top layer, they occupy a small area resulting inarea overhead. Additionally, a minimum separation is required to facilitateconnection between MIV and transistors which increases this overhead further.Towards this, we studied the alternate utilization of MIV to createMIV-transistors with varying channels. We have also presented a strategy toextract the Spice parameters of the proposed models using level 70 spiceparameters. Finally, a standard cell based gate level comparison is presentedto compare the Power, Performance and Area (PPA) metrics of the traditional twolayer 2D FDSOI transistor implementation with the proposed models. Simulationresults from standard cell designs suggest that the proposed methodology canreduce 18\% layout area on average compared to the traditional approach. Inaddition, power consumption and delay time of the standard cells are reduced by1\% and 3\% on average respectively.

FDSOI Process Based MIV-transistor Utilization for Standard Cell Designs in Monolithic 3D Integration