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We present a new formulation for parallel matrix multiplication (MM) toout-perform the standard row-column code design. This algorithm is formulatedin the MoA formalism (A Mathematics of Arrays) and combines an array view ofhardware (dimension-lifting) to extend indexing to physical memory/processingunits, with a contiguous data layout derived from static transformations. Thisview of a hardware-software model is thus a bridging model in the sense ofValiant's BSP. OpenACCcode was derived from the MoA expressions's normal form,producing optimal block sizes using the static information of types and shapes.Experiments were run on Nvidia V100 GPUs and reveal energy consumption which isquadratic in N, i.e. linear in the size of matrix. More generally this approachmay be an ideal way of formulating, optimizing, and mapping array algorithms toembedded hardware. This work builds upon recently published results of NRELscientists.  .

From array algebra to energy efficiency on GPUs: Data and hardware shapes with dimension-lifting to optimize memory-processor layouts