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High-Performance Computing (HPC) processors are nowadays integratedCyber-Physical Systems demanding complex and high-bandwidth closed-loop powerand thermal control strategies. To efficiently satisfy real-time multi-inputmulti-output (MIMO) optimal power requirements, high-end processors integratean on-die power controller system (PCS).  While traditional PCSs are based on a simple microcontroller (MCU)-classcore, more scalable and flexible PCS architectures are required to supportadvanced MIMO control algorithms for managing the ever-increasing number ofcores, power states, and process, voltage, and temperature variability.  This paper presents ControlPULP, an open-source, HW/SW RISC-V parallel PCSplatform consisting of a single-core MCU with fast interrupt handling coupledwith a scalable multi-core programmable cluster accelerator and a specializedDMA engine for the parallel acceleration of real-time power managementpolicies. ControlPULP relies on FreeRTOS to schedule a reactive power controlfirmware (PCF) application layer.  We demonstrate ControlPULP in a power management use-case targeting anext-generation 72-core HPC processor. We first show that the multi-corecluster accelerates the PCF, achieving 4.9x speedup compared to single-coreexecution, enabling more advanced power management algorithms within thecontrol hyper-period at a shallow area overhead, about 0.1% the area of amodern HPC CPU die. We then assess the PCS and PCF by designing an FPGA-based,closed-loop emulation framework that leverages the heterogeneous SoCs paradigm,achieving DVFS tracking with a mean deviation within 3% the plant's thermaldesign power (TDP) against a software-equivalent model-in-the-loop approach.Finally, we show that the proposed PCF compares favorably with anindustry-grade control algorithm under computational-intensive workloads.

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core  HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal  Emulation