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Decades of progress in energy-efficient and low-power design havesuccessfully reduced the operational carbon footprint in the semiconductorindustry. However, this has led to an increase in embodied emissions,encompassing carbon emissions arising from design, manufacturing, packaging,and other infrastructural activities. While existing research has developedtools to analyze embodied carbon at the computer architecture level fortraditional monolithic systems, these tools do not apply to near-mainstreamheterogeneous integration (HI) technologies. HI systems offer significantpotential for sustainable computing by minimizing carbon emissions through twokey strategies: ``reducing" computation by reusing pre-designed chiplet IPblocks and adopting hierarchical approaches to system design. The reuse ofchiplets across multiple designs, even spanning multiple generations ofintegrated circuits (ICs), can substantially reduce embodied carbon emissionsthroughout the operational lifespan. This paper introduces a carbon analysistool specifically designed to assess the potential of HI systems infacilitating greener VLSI system design and manufacturing approaches. The tooltakes into account scaling, chiplet and packaging yields, design complexity,and even carbon overheads associated with advanced packaging techniquesemployed in heterogeneous systems. Experimental results demonstrate that HI canachieve a reduction of embodied carbon emissions up to 70\% compared totraditional large monolithic systems. These findings suggest that HI can pavethe way for sustainable computing practices, contributing to a moreenvironmentally conscious semiconductor industry.

ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI