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In energy-constrained scenarios such as IoT applications, the primaryrequirement for System-on-Chips (SoCs) is to increase battery life. However,when performing sub/near-threshold operations, the relatively large leakagecurrent hinders Static Random Access Memory (SRAM) from normal read/writefunctionalities at the lowest possible voltage (VDDMIN). In this work, wepropose an Ultra8T SRAM to aggressively reduce VDDMIN by using a leakagedetection strategy where the safety sensing time on bitlines is quantifiedwithout any additional hardware overhead. We validate the proposed Ultra8Tusing a 256x64 array in 28nm CMOS technology. Post-simulations show successfulread operation at 0.25V with 1.11{\mu}s read delay, and the minimum energyrequired is 1.69pJ at 0.4V.

Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection